1. Field of the Invention
The present invention relates to a ferroelectric memory and an operating method therefor as well as a memory device, and more particularly, it relates to a ferroelectric memory having a ferroelectric capacitor and an operating method therefor as well as a memory device having storage means.
2. Description of the Background Art
In recent years, a ferroelectric memory has been noted as a high-speed nonvolatile memory requiring low power consumption. Therefore, the ferroelectric memory is actively researched and developed.
FIG. 25 is a representative circuit diagram of a most generally employed conventional ferroelectric memory, and FIG. 26 is a sectional view corresponding to FIG. 25. Referring to FIGS. 25 and 26, element isolation regions 102 are formed on prescribed regions of the surface of a semiconductor substrate 101 in the structure of the conventional ferroelectric memory. Source regions 103 and drain regions 104 are formed in element forming regions enclosed with the element isolation regions 102. Gate electrodes 106 forming word lines WL are formed on channel regions located between the source regions 103 and the drain regions 104 through gate insulator films 105. Bit lines (BL) 113 are electrically connected to the drain regions 104.
Lower electrodes 109 are formed on the source regions 103 through plug electrodes 108. Upper electrodes 111 constituting plate lines PL are formed on the lower electrodes 109 through ferroelectric layers 110. The lower electrodes 109, the ferroelectric layers 110 and the upper electrodes 111 form ferroelectric capacitors 112. The source and drain regions 103 and 104, the gate insulator films 105 and the gate electrodes 106 form transistors 107. The transistors 107 serve as switches for selecting memory cells 100. As shown in FIG. 25, each memory cell 100 is formed by a single transistor 107 and a single ferroelectric capacitor 112.
However, the conventional ferroelectric memory shown in FIGS. 25 and 26 having the memory cells 100 each formed by the single transistor 107 and the single ferroelectric capacitor 112 disadvantageously requires a relatively large memory cell area.
In this regard, there has been developed a simple matrix ferroelectric memory having memory cells each formed by only a single ferroelectric capacitor.
FIG. 27 is a circuit diagram of a conventional simple matrix ferroelectric memory, and FIG. 28 is a sectional view corresponding to FIG. 27. Referring to FIGS. 27 and 28, a ferroelectric layer 202 is formed on bit lines (BL) 201 in the conventional simple matrix ferroelectric memory. Word lines (WL) 203 are formed on the ferroelectric layer 202 to intersect with the bit lines 201. The bit lines 201, the ferroelectric layer 202 and the word lines 203 form ferroelectric capacitors 210. In this simple matrix ferroelectric memory, each memory cell 200 is formed by only a single ferroelectric capacitor 210, as shown in FIG. 27.
FIG. 29 is a circuit diagram for illustrating a conventional ½Vcc method of applying voltages to the simple matrix ferroelectric memory in writing, and FIG. 30 is a circuit diagram for illustrating a conventional ⅓Vcc method of applying voltages to the simple matrix ferroelectric memory in writing.
Referring to FIG. 29, a power supply voltage Vcc is applied across a bit line BL1 and a word line WL1 connected with a selected memory cell (hereinafter also referred to as “selected cell”) 200 in the conventional ½Vcc method, in order to drive the selected cell 200. In other words, the power supply voltage Vcc and a voltage of 0 V are applied to the word line WL1 and the bit line BL1 respectively. Further, the voltage of 0 V is applied to word lines WL0 and WL2 connected with non-selected memory cells (hereinafter also referred to as “non-selected cells”) 200, and a voltage of ½Vcc is applied to bit lines BL0 and BL2 connected with the non-selected cells 200. Thus, the power supply voltage Vcc is applied to the selected cell 200 while the voltage ½Vcc is applied to the non-selected cells 200.
Referring to FIG. 30, a power supply voltage Vcc is applied to the word line WL1 while a voltage of 0 V is applied to the bit line BL1 in the conventional ⅓Vcc method. Further, a voltage of ⅓Vcc is applied to the word lines WL0 and WL2 connected with the non-selected memory cells (non-selected cells) 200, and a voltage of ⅔Vcc is applied to the bit lines BL0 and BL2 connected with the non-selected cells 200. Thus, the power supply voltage Vcc is applied to the selected cell 200 while the voltage ⅓Vcc is applied to the non-selected cells 200.
In each of the aforementioned cases, polarization inversion must be sufficiently saturated with respect to the ferroelectric layer 202 (see FIG. 28) of the selected cell 200 while polarized states must be substantially unchanged with respect to the ferroelectric layers 202 of the non-selected cells 200.
At present, however, the angular shape of ferroelectric hysteresis loop is so insufficient that information (quantity of charges) is lost by the so-called disturbance if the voltage of ½Vcc or ⅓Vcc is continuously unidirectionally applied to the non-selected cells 200, as shown in FIG. 31. Information written in the non-selected cells 200 is lost due to such disturbance, and hence the ferroelectric memory is hard to use in this case. At present, therefore, it is regarded as difficult to put the simple matrix ferroelectric memory shown in FIGS. 27 and 28 into practice.
Comparing the conventional ⅓Vcc method with the conventional ½Vcc method, potential difference applied to the non-selected cells 200 of the simple matrix ferroelectric memory can be suppressed to ⅓Vcc according to the conventional ⅓Vcc method. According to the ⅓Vcc method, therefore, reduction of the polarization quantity of the non-selected cells 200 can be more suppressed in the simple matrix ferroelectric memory as compared with the ½Vcc method.
In the conventional ⅓Vcc method, however, voltages of ⅓Vcc (=k) and ⅔Vcc (=2k) must be applied to the non-selected word lines WL0 and WL2 and the non-selected bit lines BL0 and BL2 respectively in order to set potential difference applied to the non-selected memory cells (non-selected cells) 200 to ⅓Vcc. In this case, four types of potentials Vcc (=3k), ⅔Vcc (=2k), ⅓Vcc (=1k) and 0 V must be selectively applied when writing data of “1” or “0” in the selected cell 200. Therefore, the simple matrix ferroelectric memory requires a power supply system generating the aforementioned four types of potentials. Further, the simple matrix ferroelectric memory also requires a system for selectively transmitting the four types of potentials generated by the power supply system to the bit lines BL0 to BL2 and the word lines WL0 to WL2. Therefore, the power supply system and the system selectively transmitting the potentials generated by the power supply system to the memory cells 200 are disadvantageously complicated. Consequently, it is disadvantageously difficult to save the area, increase the speed and reduce the power in the conventional simple matrix ferroelectric memory.